In my previous U.S. Pat. No. 4,185,275 issued Jan. 22, 1980, there is disclosed a multi-stage digital-to-analog converter which employs a sampling capacitor for each stage of coding. A reference terminal of the sampling capacitor is connected to a tap of a precision resistive divider providing a binary-weighted reference voltage for the stage. The other terminal of the sampling capacitor receives the input sample to be quantized by the stage. A comparator compares the analog sample that is input to the stage with the reference voltage for the stage. If the input sample is at a higher voltage than the reference voltage at the tap, a flip-flop is set for the stage and the reference terminal of the sampling capacitor is disconnected from the reference tap and clamped to ground to "subtract" an increment from the sample. If the voltage of the input analog sample is lower than the reference voltage, the flip-flop is not set and the reference terminal of the capacitor is not clamped to ground. In either event, the input terminal of the sampling capacitor is then connected to the input of the next stage where the process is repeated, except that the reference terminal of the second stage's capacitor is connected to a tap of the resistive divider offering a lower, binary-weighted reference voltage.
While the foregoing circuit is satisfactory for many applications, it would be advantageous to employ integrated CMOS or NMOS technology. However, it is difficult to provide a precision resistive divider using that technology, moreover, even were it possible to provide an integrated precision voltage divider, each comparator of the prior art circuit would receive different reference voltage inputs from the divider causing possible variation in the performance characteristics of the comparator. All of the comparators should have the same sensitivity and accuracy in order to maintain the monotonicity of the encoding and decoding levels.